Invention Grant
- Patent Title: Failsafe and tolerant driver architecture and method
- Patent Title (中): 故障安全和容忍驱动程序架构和方法
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Application No.: US12610275Application Date: 2009-10-31
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Publication No.: US07834653B1Publication Date: 2010-11-16
- Inventor: Pankaj Kumar , Pramod Elamannu Parameswaran , Makeshwar Kothandaraman , Vani Deshpande
- Applicant: Pankaj Kumar , Pramod Elamannu Parameswaran , Makeshwar Kothandaraman , Vani Deshpande
- Applicant Address: US CA Milpitas
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA Milpitas
- Agent Raj Abhyanker, PC
- Main IPC: H03K19/007
- IPC: H03K19/007

Abstract:
A method includes controllably utilizing a control signal generated by an Input/Output (IO) core to isolate a current path from an external voltage supplied through an IO pad to a supply voltage by transmitting a same voltage at an input terminal of a transistor, configured to be part of a number of cascaded transistors of an IO driver of an interface circuit, to an output terminal thereof during a failsafe mode of operation and a tolerant mode of operation. The method also includes feeding back an appropriate voltage to a floating node created by the isolation of the current path, and controlling a voltage across each transistor of the number of cascaded transistors to be within an upper tolerable limit thereof through an application of a gate voltage to each transistor derived from the supply voltage or the external voltage supplied through the IO pad.
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