Invention Grant
- Patent Title: Display processing line buffers incorporating pipeline overlap
- Patent Title (中): 显示处理线缓冲器结合管道重叠
-
Application No.: US11510045Application Date: 2006-08-25
-
Publication No.: US07834873B2Publication Date: 2010-11-16
- Inventor: Sreenath Kurupati
- Applicant: Sreenath Kurupati
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06T15/00
- IPC: G06T15/00

Abstract:
Apparatus, systems and methods for display processing line buffers incorporating pipeline overlap are disclosed. For example, an apparatus is disclosed including processing logic to use pixel processing algorithms to process a pixel value of a first portion of an image, and line buffers coupled to the processing logic. The line buffers to hold at least some pixel values of other portions of the image adjacent to the first portion. Where the pixel values of the other portions of the image held by the line buffers correspond to pixel values of the adjacent portions of the image that are to be convolved by the pixel processing algorithms with the pixel value of the first portion. Other implementations are also disclosed.
Public/Granted literature
- US20080049037A1 Display processing line buffers incorporating pipeline overlap Public/Granted day:2008-02-28
Information query
IPC分类:
G | 物理 |
G06 | 计算;推算或计数 |
G06T | 一般的图像数据处理或产生 |
G06T15/00 | 3D〔三维〕图像的加工 |