Invention Grant
US07834873B2 Display processing line buffers incorporating pipeline overlap 有权
显示处理线缓冲器结合管道重叠

Display processing line buffers incorporating pipeline overlap
Abstract:
Apparatus, systems and methods for display processing line buffers incorporating pipeline overlap are disclosed. For example, an apparatus is disclosed including processing logic to use pixel processing algorithms to process a pixel value of a first portion of an image, and line buffers coupled to the processing logic. The line buffers to hold at least some pixel values of other portions of the image adjacent to the first portion. Where the pixel values of the other portions of the image held by the line buffers correspond to pixel values of the adjacent portions of the image that are to be convolved by the pixel processing algorithms with the pixel value of the first portion. Other implementations are also disclosed.
Public/Granted literature
Information query
Patent Agency Ranking
0/0