A semiconductor memory device includes a plurality of banks, each configured to receive a bank operation control signal and perform predetermined operations in response to the received bank operation control signal, a plurality of bank control blocks, each configured to receive a bank sequential signal and generate the plurality of bank operation control signals in response to enable periods of the received bank sequential signal, and a bank sequential signal generating block configured to generate the plurality of bank sequential signals each having a multiplicity of enable periods that are sequential in response to a command signal.