A semiconductor memory apparatus includes a MOS transistor configured to be supplied with a first voltage through a bulk terminal thereof. The semiconductor memory apparatus also includes a current control unit configured to be connected to a source terminal of the MOS transistor, receive a power down mode enable signal and a self refresh mode enable signal, apply a second voltage to the source terminal during a power down mode or a self refresh mode, and apply the first voltage to the source terminal during modes other than the power down mode and the self refresh mode.