Invention Grant
US07836274B2 Method and system for combining page buffer list entries to optimize caching of translated addresses
有权
用于组合页面缓冲区列表条目以优化翻译地址的缓存的方法和系统
- Patent Title: Method and system for combining page buffer list entries to optimize caching of translated addresses
- Patent Title (中): 用于组合页面缓冲区列表条目以优化翻译地址的缓存的方法和系统
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Application No.: US11515563Application Date: 2006-09-05
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Publication No.: US07836274B2Publication Date: 2010-11-16
- Inventor: Caitlin Bestler
- Applicant: Caitlin Bestler
- Applicant Address: US CA Irvine
- Assignee: Broadcom Corporation
- Current Assignee: Broadcom Corporation
- Current Assignee Address: US CA Irvine
- Agency: McAndrews, Held & Malloy, Ltd.
- Main IPC: G06F9/30
- IPC: G06F9/30

Abstract:
Certain aspects of a method and system for combining page buffer list entries (PBLEs) to optimize caching of translated addresses are disclosed. Aspects of a method may include encoding at least two page buffer list entries in a remote direct memory access (RDMA) memory map into at least two contiguous memory locations by utilizing a remainder of a physical address corresponding to the two page buffer list entries. The first memory location of the two contiguous memory locations may comprise a base address and a contiguous length of the first page buffer list entry. The second memory location of the two contiguous memory locations may comprise a virtual address and a contiguous length of the second page buffer list entry.
Public/Granted literature
- US20080059600A1 Method and system for combining page buffer list entries to optimize caching of translated addresses Public/Granted day:2008-03-06
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