Invention Grant
- Patent Title: Clock regeneration circuit
- Patent Title (中): 时钟再生电路
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Application No.: US11924998Application Date: 2007-10-26
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Publication No.: US07836323B2Publication Date: 2010-11-16
- Inventor: Kensuke Fujimura , Naoki Tanahashi
- Applicant: Kensuke Fujimura , Naoki Tanahashi
- Applicant Address: JP
- Assignee: Sanyo Electric Co., Ltd.
- Current Assignee: Sanyo Electric Co., Ltd.
- Current Assignee Address: JP
- Agency: Cantor Colburn LLP
- Priority: JP2006-290910 20061026
- Main IPC: G01D1/00
- IPC: G01D1/00

Abstract:
There is disclosed a clock regeneration circuit having a PCR buffer including a register which buffers a PCR extracted from a transmission signal, a counter which counts a reception side reference clock CKr, an STC buffer including a register which buffers a counted value of the counter, and a CPU which generates a signal indicating a difference between a transmission side reference clock and the reception side reference clock CKr based on values held in the PCR buffer and the STC buffer. If, at this point, a new PCR is input before the values held in the PCR buffer and the STC buffer are read by the CPU, the PCR buffer and the STC buffer are not updated.
Public/Granted literature
- US20080100359A1 CLOCK REGENERATION CIRCUIT Public/Granted day:2008-05-01
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