Invention Grant
- Patent Title: Design structure for low voltage applications in an integrated circuit
- Patent Title (中): 集成电路中低压应用的设计结构
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Application No.: US11851138Application Date: 2007-09-06
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Publication No.: US07839206B2Publication Date: 2010-11-23
- Inventor: Wagdi W. Abadeer , Albert M. Chu
- Applicant: Wagdi W. Abadeer , Albert M. Chu
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Roberts Mlotkowski Safran & Cole, P.C.
- Agent David Cain
- Main IPC: G05F1/46
- IPC: G05F1/46

Abstract:
A design structure that includes at least one tunneling device voltage reference circuit for use in low voltage applications is disclosed. The tunneling device voltage reference circuit includes a pair of voltage dividing device stacks, one having a linear voltage output and the other having a non-linear voltage output. A feedback circuit supplies a regulated voltage to each of the voltage dividing stacks so that the output voltages of the two device stacks equalize. Once the feedback circuit has locked, any one of the device stack output voltages and the regulated voltage may be used as a voltage reference.
Public/Granted literature
- US20080169867A1 DESIGN STRUCTURE FOR LOW VOLTAGE APPLICATIONS IN AN INTEGRATED CIRCUIT Public/Granted day:2008-07-17
Information query
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