Invention Grant
US07839693B1 Method of fabricating CMOS-compatible non-volatile memory cell with lateral inter-poly programming layer
有权
制造具有横向多层间编程层的CMOS兼容非易失性存储单元的方法
- Patent Title: Method of fabricating CMOS-compatible non-volatile memory cell with lateral inter-poly programming layer
- Patent Title (中): 制造具有横向多层间编程层的CMOS兼容非易失性存储单元的方法
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Application No.: US12683585Application Date: 2010-01-07
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Publication No.: US07839693B1Publication Date: 2010-11-23
- Inventor: Sunhom Paak , Boon Y. Ang , Hsung J. Im , Daniel Gitlin
- Applicant: Sunhom Paak , Boon Y. Ang , Hsung J. Im , Daniel Gitlin
- Applicant Address: US CA San Jose
- Assignee: Xilinix, Inc.
- Current Assignee: Xilinix, Inc.
- Current Assignee Address: US CA San Jose
- Agent Scott Hewett; LeRoy D. Maunu; Lois D. Cartier
- Main IPC: G11C16/06
- IPC: G11C16/06
Abstract:
An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.
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