Invention Grant
- Patent Title: Carbon nanotube transistors on a silicon or SOI substrate
- Patent Title (中): 硅或SOI衬底上的碳纳米管晶体管
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Application No.: US12700479Application Date: 2010-02-04
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Publication No.: US07842955B2Publication Date: 2010-11-30
- Inventor: Ashesh Parikh , Andrew Marshall
- Applicant: Ashesh Parikh , Andrew Marshall
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L29/15
- IPC: H01L29/15 ; H01L29/76 ; H01L29/94

Abstract:
A method of forming a single wall thickness (SWT) carbon nanotube (CNT) transistor with a controlled diameter and chirality is disclosed. A photolithographically defined single crystal silicon seed layer is converted to a single crystal silicon carbide seed layer. A single layer of graphene is formed on the top surface of the silicon carbide. The SWT CNT transistor body is grown from the graphene layer in the presence of carbon containing gases and metal catalyst atoms. Silicided source and drain regions at each end of the silicon carbide seed layer provide catalyst metal atoms during formation of the CNT. The diameter of the SWT CNT is established by the width of the patterned seed layer. A conformally deposited gate dielectric layer and a transistor gate over the gate dielectric layer complete the CNT transistor. CNT transistors with multiple CNT bodies, split gates and varying diameters are also disclosed.
Public/Granted literature
- US20100133512A1 METHOD FOR FABRICATING CARBON NANOTUBE TRANSISTORS ON A SILICON OR SOI SUBSTRATE Public/Granted day:2010-06-03
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