Invention Grant
- Patent Title: Method and structure for improving device performance variation in dual stress liner technology
- Patent Title (中): 双应力衬垫技术改进装置性能变化的方法和结构
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Application No.: US12328358Application Date: 2008-12-04
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Publication No.: US07843024B2Publication Date: 2010-11-30
- Inventor: Dureseti Chidambarrao , Brian J. Greene
- Applicant: Dureseti Chidambarrao , Brian J. Greene
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Joseph P. Abate, Esq.
- Main IPC: H01L29/82
- IPC: H01L29/82 ; H01L21/338
Abstract:
A method and semiconductor structure that overcome the dual stress liner boundary problem, without significantly increasing the overall size of the integrated circuit, are provided. In accordance with the present invention, the dual stress liner boundary or gap therebetween is forced to land on a neighboring dummy gate region. By forcing the dual stress liner boundary or gap between the liners to land on the dummy gate region, the large stresses associated with the dual stress liner boundary or gap are transferred to the dummy gate region, not the semiconductor substrate. Thus, the impact of the dual stress liner boundary on the nearest neighboring FET is reduced. Additionally, benefits of device variability and packing density are achieved utilizing the present invention.
Public/Granted literature
- US20090079011A1 METHOD AND STRUCTURE FOR IMPROVING DEVICE PERFORMANCE VARIATION IN DUAL STRESS LINER TECHNOLOGY Public/Granted day:2009-03-26
Information query
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