A phase lock loop apparatus is disclosed. The phase lock loop apparatus comprises a phase detecting module, a logic processing module, a charge pump and loop filter (CPLF), and a voltage control oscillator. The phase detecting module detects the phase difference between an input data signal and a clock signal to generate a first index signal. The logic processing module performs a high-frequency dithering process to the first index signal to generate a second index signal. The CPLF adjusts a control voltage according to the first index signal and the second index signal, and outputs the adjusted control voltage. The voltage control oscillator adjusts the frequency or phase of the clock signal and outputs the adjusted clock signal to the phase detecting module. The frequency of the second index signal is equal to or larger than the frequency of the first index signal.