Invention Grant
US07843721B1 Memory cell including an emitter follower and emitter follower sensing scheme and method of reading data therefrom
失效
包括射极跟随器和射极跟随器感测方案的存储单元以及从其读取数据的方法
- Patent Title: Memory cell including an emitter follower and emitter follower sensing scheme and method of reading data therefrom
- Patent Title (中): 包括射极跟随器和射极跟随器感测方案的存储单元以及从其读取数据的方法
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Application No.: US12284037Application Date: 2008-09-18
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Publication No.: US07843721B1Publication Date: 2010-11-30
- Inventor: Richard K. Chou , Damodar R. Thummalapally
- Applicant: Richard K. Chou , Damodar R. Thummalapally
- Applicant Address: US CA Los Gatos
- Assignee: SuVolta, Inc.
- Current Assignee: SuVolta, Inc.
- Current Assignee Address: US CA Los Gatos
- Agent Darryl G. Walker
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
A memory device including a static random access memory (SRAM) cell comprising junction field effect transistors (JFETs) has been disclosed. The memory cell includes a first bipolar junction transistor (BJT) for driving a bit line at logic levels having a potential outside the potential range in which the SRAM cell operates. An amplifier including a level translator circuit provides a level shifting operation on the data provided by the bit line to provide level shifted data having a voltage swing within the potential range in which the SRAM cell operates. The level translator circuit includes a second BJT. In this way, fast read operation of a SRAM cell comprising JFETs may be provided.
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