Invention Grant
US07846826B2 Method of manufacturing a semiconductor device with multilayer sidewall
有权
制造具有多层侧壁的半导体器件的方法
- Patent Title: Method of manufacturing a semiconductor device with multilayer sidewall
- Patent Title (中): 制造具有多层侧壁的半导体器件的方法
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Application No.: US12246908Application Date: 2008-10-07
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Publication No.: US07846826B2Publication Date: 2010-12-07
- Inventor: Kiyonori Oyu , Kensuke Okonogi
- Applicant: Kiyonori Oyu , Kensuke Okonogi
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory Inc.
- Current Assignee: Elpida Memory Inc.
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2004-301612 20041015
- Main IPC: H01L21/3205
- IPC: H01L21/3205 ; H01L21/4763

Abstract:
A gate dielectric film, a poly-silicon film, a film of a refractory metal such as tungsten, and a gate cap dielectric film are sequentially laminated on a semiconductor substrate. The gate cap dielectric film and the refractory metal film are selectively removed by etching. Thereafter, a double protection film including a silicon nitride film and a silicon oxide film is formed on side surfaces of the gate cap dielectric film, the refractory metal film, and the poly-silicon film. The poly-silicon film is etched using the double protection film as a mask. Thereafter, the semiconductor substrate is light oxidized to form a silicon oxide film on side surfaces of the poly-silicon film. Accordingly, a junction leakage of a MOSFET having a gate electrode of a poly-metal structure, particularly, a memory cell transistor of a DRAM, can be further reduced.
Public/Granted literature
- US20090042380A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2009-02-12
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