Invention Grant
- Patent Title: Method and apparatus for nano probing a semiconductor chip
- Patent Title (中): 用于纳米探测半导体芯片的方法和装置
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Application No.: US12180989Application Date: 2008-07-28
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Publication No.: US07847575B2Publication Date: 2010-12-07
- Inventor: Ronald M. Potok , Gregory A. Dabney , Abdullah M. Yassine
- Applicant: Ronald M. Potok , Gregory A. Dabney , Abdullah M. Yassine
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Ditthavong, Mori & Steiner, P.C.
- Main IPC: G01R31/26
- IPC: G01R31/26

Abstract:
Various methods and apparatus for electrically probe testing a semiconductor chip with circuit perturbation are disclosed. In one aspect, a method of testing is provided that includes contacting a first nano probe to a conductor structure on a first side of a semiconductor chip. The semiconductor chip has plural circuit structures. A external stimulus is applied to a selected portion of the first side of the semiconductor chip to perturb at least one of the plural circuit structures. The semiconductor chip is caused to perform a test pattern during the application of the external stimulus. An electrical characteristic of the semiconductor chip is sensed with the first nano probe during performance of the test pattern.
Public/Granted literature
- US20100019786A1 Method and Apparatus for Nano Probing a Semiconductor Chip Public/Granted day:2010-01-28
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