Invention Grant
- Patent Title: Algorithmic reactive testbench for analog designs
- Patent Title (中): 用于模拟设计的算法反应测试台
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Application No.: US11899215Application Date: 2007-09-05
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Publication No.: US07853908B2Publication Date: 2010-12-14
- Inventor: Jang Dae Kim , Steve A. Martinez , Satya N. Mishra , Alan P. Bucholz , Hui X. Li , Rajesh R. Berigei
- Applicant: Jang Dae Kim , Steve A. Martinez , Satya N. Mishra , Alan P. Bucholz , Hui X. Li , Rajesh R. Berigei
- Applicant Address: US CA Santa Clara
- Assignee: National Semiconductor Corporation
- Current Assignee: National Semiconductor Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Dergosits & Noah LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/45

Abstract:
An Algorithmic Reactive Testbench (ART) system is provided for the simulation/verification of an analog integrated circuit design. The ART system is a high level simulation/verification environment with a user program in which one or more analog testbenches are instantiated and operated as prescribed in an algorithmic reactive testbench program, and the properties of the unit testbenches (test objects) can be influenced by prior analysis of themselves or other tests. The test object may also contain various properties including information reflecting the status of the test object. The modification of a property of a test object is an act of communication in the ART system from the algorithmic reactive testbench program to the test object.
Public/Granted literature
- US20090064063A1 Algorithmic reactive testbench for analog designs Public/Granted day:2009-03-05
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