Invention Grant
US07855120B2 Methods for forming resistors including multiple layers for integrated circuit devices
有权
用于形成用于集成电路器件的多层电阻器的方法
- Patent Title: Methods for forming resistors including multiple layers for integrated circuit devices
- Patent Title (中): 用于形成用于集成电路器件的多层电阻器的方法
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Application No.: US11780026Application Date: 2007-07-19
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Publication No.: US07855120B2Publication Date: 2010-12-21
- Inventor: Je-Min Park , Yoo-Sang Hwang
- Applicant: Je-Min Park , Yoo-Sang Hwang
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Myers Bigel Sibley & Sajovec, P.A.
- Priority: KR10-2003-0075750 20031029
- Main IPC: H01L21/20
- IPC: H01L21/20

Abstract:
Methods of forming an integrated circuit device may include forming an insulating layer on an integrated circuit substrate, forming a first conductive layer on the insulating layer, and forming a second conductive layer on the first conductive layer so that the first conductive layer is between the second conductive layer and the insulating layer. Moreover, the first conductive layer may be a layer of a first material, the second conductive layer may be a layer of a second material, and the first and second materials may be different. A hole may be formed in the second conductive layer so that portions of the first conductive layer are exposed through the hole. After forming the hole in the second conductive layer, the first and second conductive layers may be patterned so that portions of the first and second conductive layers surrounding portions of the first conductive layer exposed through the hole are removed while maintaining portions of the first conductive layer previously exposed through the hole.
Public/Granted literature
- US20070259494A1 Methods for Forming Resistors Including Multiple Layers for Integrated Circuit Devices Public/Granted day:2007-11-08
Information query
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