Invention Grant
US07855135B2 Method to reduce parastic capacitance in a metal high dielectric constant (MHK) transistor
有权
降低金属高介电常数(MHK)晶体管中的寄生电容的方法
- Patent Title: Method to reduce parastic capacitance in a metal high dielectric constant (MHK) transistor
- Patent Title (中): 降低金属高介电常数(MHK)晶体管中的寄生电容的方法
-
Application No.: US12539860Application Date: 2009-08-12
-
Publication No.: US07855135B2Publication Date: 2010-12-21
- Inventor: Leland Chang , Isaac Lauer , Renee T. Mo , Jeffrey W. Sleight
- Applicant: Leland Chang , Isaac Lauer , Renee T. Mo , Jeffrey W. Sleight
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Harrington & Smith
- Main IPC: H01L21/3205
- IPC: H01L21/3205 ; H01L21/4763 ; H01L21/336

Abstract:
A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer.
Public/Granted literature
Information query
IPC分类: