Invention Grant
- Patent Title: Molded ultra thin semiconductor die packages, systems using the same, and methods of making the same
- Patent Title (中): 成型超薄半导体管芯封装,使用其的系统及其制造方法
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Application No.: US12200819Application Date: 2008-08-28
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Publication No.: US07855439B2Publication Date: 2010-12-21
- Inventor: Yong Liu
- Applicant: Yong Liu
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Agency: Townsend and Townsend and Crew LLP
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L23/02 ; H01L23/48 ; H01L23/28 ; H01L21/48 ; H01L21/50

Abstract:
Disclosed are molded ultra-thin semiconductor die packages, systems that incorporate such packages, and methods of making such packages. An exemplary package comprises a leadframe having an aperture formed between the leadframe's first and second surfaces, and a plurality of leads disposed adjacent to the aperture. The package further comprises a semiconductor disposed in the aperture of the leadframe with its top surface substantially flush with the leadframe's first surface, and at least one gap between at least one side surface of the semiconductor die and at least one lead of the leadframe. A body of electrically insulating material is disposed in the at least one gap. A plurality of conductive members interconnect leads of the leadframe with conductive regions on the die's top surface, with at least one conductive member having a portion disposed over at least a portion of the body of insulating material.
Public/Granted literature
- US20100052119A1 Molded Ultra Thin Semiconductor Die Packages, Systems Using the Same, and Methods of Making the Same Public/Granted day:2010-03-04
Information query
IPC分类: