Mixer topologies that have sufficiently high IIP2 and sufficiently low quadrature error to make zero IF receivers possible without special calibration techniques. This simplifies the receiver, avoids circuit startup delay and provides more stable performance over time and temperature. The methodology to achieve this performance in preferred embodiments consists of as many as three elements: (a) a high power local oscillator buffer circuit capable of driving low impedance loads coupled to the bases of the bipolar mixer transistors, (b) an optimized bias block for the mixer core and (c) incorporating two or more electronically programmable quad sections and selecting the best quad for use. Other types of transistors may also be used.