Invention Grant
- Patent Title: Multi-layer stacked wafer level semiconductor package module
- Patent Title (中): 多层堆叠晶圆级半导体封装模块
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Application No.: US12048304Application Date: 2008-03-14
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Publication No.: US07859102B2Publication Date: 2010-12-28
- Inventor: Sung Min Kim , Chang Jun Park , Kwon Whan Han , Seong Cheol Kim , Hyeong Seok Choi , Ha Na Lee
- Applicant: Sung Min Kim , Chang Jun Park , Kwon Whan Han , Seong Cheol Kim , Hyeong Seok Choi , Ha Na Lee
- Applicant Address: KR Kyoungki-do
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Kyoungki-do
- Agency: Ladas & Parry LLP
- Priority: KR10-2008-0000303 20080102
- Main IPC: H01L23/36
- IPC: H01L23/36

Abstract:
A stacked wafer level semiconductor package module includes a semiconductor chip module including first and second semiconductor chips each having a rectangular shape. The first semiconductor chip has first pads disposed along a first short side of a lower surface thereof. The second semiconductor chip has second pads disposed along a first short side of a lower surface thereof. The first and second semiconductor chips are stacked so as to expose the first pad and the second pad on one side of the stacked first and second semiconductor chips. The package also includes a substrate having a first connection pad facing the first pad and a second connection pad facing the second pad. The package also includes a first connection member for connecting the first pad to the first connection pad, and a second connection member for connecting the second pad to the second connection pad.
Public/Granted literature
- US20090166853A1 MULTI-LAYER STACKED WAFER LEVEL SEMICONDUCTOR PACKAGE MODULE Public/Granted day:2009-07-02
Information query
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