Invention Grant
- Patent Title: PLL circuit with improved phase difference detection
- Patent Title (中): PLL电路具有改进的相位差检测
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Application No.: US12111458Application Date: 2008-04-29
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Publication No.: US07859344B2Publication Date: 2010-12-28
- Inventor: Toshiya Uozumi , Keisuke Ueda , Mitsunori Samata , Satoru Yamamoto , Russell P Mohn , Aleksander Dec , Ken Suyama
- Applicant: Toshiya Uozumi , Keisuke Ueda , Mitsunori Samata , Satoru Yamamoto , Russell P Mohn , Aleksander Dec , Ken Suyama
- Applicant Address: JP Kanagawa US NY Tarrytown
- Assignee: Renesas Electronics Corporation,Epoch Microelectronics, Inc.
- Current Assignee: Renesas Electronics Corporation,Epoch Microelectronics, Inc.
- Current Assignee Address: JP Kanagawa US NY Tarrytown
- Agency: Mattingly & Malur, P.C.
- Main IPC: H03L7/00
- IPC: H03L7/00

Abstract:
In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.
Public/Granted literature
- US20090267664A1 PLL CIRCUIT Public/Granted day:2009-10-29
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