Invention Grant
US07859438B2 Digital signal coding method and apparatus, digital signal decoding apparatus; digital signal arithmetic coding method, and digital signal arithmetic decoding method
有权
数字信号编码方法及装置，数字信号解码装置; 数字信号算术编码方法和数字信号算术解码方法
- Patent Title: Digital signal coding method and apparatus, digital signal decoding apparatus; digital signal arithmetic coding method, and digital signal arithmetic decoding method
- Patent Title (中): 数字信号编码方法及装置，数字信号解码装置; 数字信号算术编码方法和数字信号算术解码方法
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Application No.: US12367266Application Date: 2009-02-06
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Publication No.: US07859438B2Publication Date: 2010-12-28
- Inventor: Shunichi Sekiguchi , Yoshihisa Yamada , Kohtaro Asai
- Applicant: Shunichi Sekiguchi , Yoshihisa Yamada , Kohtaro Asai
- Applicant Address: JP Tokyo
- Assignee: Mitsubihsi Denki Kabushiki Kaisha
- Current Assignee: Mitsubihsi Denki Kabushiki Kaisha
- Current Assignee Address: JP Tokyo
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Priority: JP2002-124114 20020425
- Main IPC: H03M7/00
- IPC: H03M7/00
Abstract:
In a bit stream syntax containing compressed video slice data for compressed video data of a slice structure, a slice header for compressed video slice data has attached thereto a slice start code, a register reset flag indicating whether a register value, which designates a status of a codeword occurring in an arithmetic coding process, should be reset in the next transmission unit, an initial register value which indicates a register value to be used to start arithmetic coding/decoding to build/decompose the next transmission unit, only when the register reset flag indicates that the register should not be reset.
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