A storage controller that operates under elevated temperature conditions includes a memory, a memory controller, and a CPU that detects a temperature of the memory controller has exceeded a threshold while operating at a first frequency and responsively places the memory into self-refresh mode, reduces the memory controller frequency to a second frequency, and then takes the memory out of self-refresh mode. The clock frequency of a bus bridge or communications link circuit may also be reduced when their temperatures exceed a threshold. The bus bridge may deny access to requestors of access to the memory while the frequency is being reduced. Message transfers on a communications link between redundant storage controllers in a system may be suspended while the link frequency is being reduced. Finally, the system may fail over to one controller while the other controller reduces the frequencies and then fail back.