Invention Grant
- Patent Title: Fabrication method of semiconductor integrated circuit device
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Application No.: US12836432Application Date: 2010-07-14
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Publication No.: US07861912B2Publication Date: 2011-01-04
- Inventor: Hiroshi Maki , Yukio Tani
- Applicant: Hiroshi Maki , Yukio Tani
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Antonelli, Terry, Stout & Kraus, LLP.
- Priority: JP2003-327046 20030919
- Main IPC: B23K31/02
- IPC: B23K31/02

Abstract:
Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage.
Public/Granted literature
- US20100279464A1 FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2010-11-04
Information query
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