Invention Grant
- Patent Title: Low cost bumping and bonding method for stacked die
- Patent Title (中): 堆叠模具的低成本碰撞和接合方法
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Application No.: US12242492Application Date: 2008-09-30
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Publication No.: US07863092B1Publication Date: 2011-01-04
- Inventor: Raghunandan Chaware , Arifur Rahman
- Applicant: Raghunandan Chaware , Arifur Rahman
- Applicant Address: US CA San Jose
- Assignee: Xilinx, Inc.
- Current Assignee: Xilinx, Inc.
- Current Assignee Address: US CA San Jose
- Agent Michael R. Hardaway; Thomas George; LeRoy D. Maunu
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/48 ; H01L21/50

Abstract:
Disclosed is a method of fabricating an integrated circuit assembly in which a plurality of mother dice having a plurality of through-die vias (TDVs) are formed in the first (active) surface of a semiconductor wafer, a substrate is attached to the active surface of the wafer, the second (inactive) surface is back-ground to expose one end of the through-die vias, a plurality of daughter dice are mounted to the inactive surface of the wafer, each daughter die being electrically coupled to a mother die, and the mother dice are then singulated. Attaching the substrate can be accomplished by adhering a glass wafer carrier to the wafer. The wafer carrier allows handling of the wafer during back-grinding the inactive surface, forming under-bump metal (UBM) pads on the TDVs and attaching the daughter dice.
Information query
IPC分类: