Invention Grant
US07863126B2 Fabrication of a CMOS structure with a high-k dielectric layer oxidizing an aluminum layer in PFET region
有权
在PFET区域中制造具有氧化铝层的高k电介质层的CMOS结构
- Patent Title: Fabrication of a CMOS structure with a high-k dielectric layer oxidizing an aluminum layer in PFET region
- Patent Title (中): 在PFET区域中制造具有氧化铝层的高k电介质层的CMOS结构
-
Application No.: US12120658Application Date: 2008-05-15
-
Publication No.: US07863126B2Publication Date: 2011-01-04
- Inventor: Dae-Gyu Park , Michael P. Chudzik , Vijay Narayanan , Vamsi Paruchuri
- Applicant: Dae-Gyu Park , Michael P. Chudzik , Vijay Narayanan , Vamsi Paruchuri
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent George Sai-Halasz; Louis J. Percello
- Main IPC: H01L21/441
- IPC: H01L21/441
Abstract:
A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of an Al layer over both the NFET device and the PFET device. The method further involves a blanket disposition of a shared gate metal layer over the Al layer. When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, while in the NFET device the Al becomes a region of the metal gate.
Public/Granted literature
- US20090283838A1 Fabrication of self-aligned CMOS structure Public/Granted day:2009-11-19
Information query
IPC分类:
