Invention Grant
US07863136B2 Method of manufacturing integrated circuits including a FET with a gate spacer and a fin
有权
制造集成电路的方法，该集成电路包括具有栅极间隔物和鳍的FET
- Patent Title: Method of manufacturing integrated circuits including a FET with a gate spacer and a fin
- Patent Title (中): 制造集成电路的方法，该集成电路包括具有栅极间隔物和鳍的FET
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Application No.: US12242039Application Date: 2008-09-30
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Publication No.: US07863136B2Publication Date: 2011-01-04
- Inventor: Matthias Goldbach , Jessica Hartwich , Lars Dreeskornfeld , Arnd Scholz , Tobias Mono
- Applicant: Matthias Goldbach , Jessica Hartwich , Lars Dreeskornfeld , Arnd Scholz , Tobias Mono
- Applicant Address: DE Munich
- Assignee: Qimonda AG
- Current Assignee: Qimonda AG
- Current Assignee Address: DE Munich
- Agency: Dicke, Billig & Czaja, PLLC
- Main IPC: H01L21/336
- IPC: H01L21/336
Abstract:
A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.
Public/Granted literature
- US20100078711A1 METHOD OF MANUFACTURING INTEGRATED CIRCUITS INCLUDING A FET WITH A GATE SPACER Public/Granted day:2010-04-01
Information query
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