Invention Grant
- Patent Title: Semiconductor die separation method
- Patent Title (中): 半导体芯片分离方法
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Application No.: US12323288Application Date: 2008-11-25
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Publication No.: US07863159B2Publication Date: 2011-01-04
- Inventor: Reynaldo Co , DeAnn Eileen Melcher , Weiping Pan , Grant Villavicencio
- Applicant: Reynaldo Co , DeAnn Eileen Melcher , Weiping Pan , Grant Villavicencio
- Applicant Address: US CA Scotts Valley
- Assignee: Vertical Circuits, Inc.
- Current Assignee: Vertical Circuits, Inc.
- Current Assignee Address: US CA Scotts Valley
- Agency: Haynes Beffel & Wolfeld LLP
- Agent Bill Kennedy
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets. Subsequent to the first cutting procedure, and prior to the second cutting procedure, additional die preparation procedures that are sensitive to die shift may be carried out.
Public/Granted literature
- US20090315174A1 Semiconductor Die Separation Method Public/Granted day:2009-12-24
Information query
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