Invention Grant
US07863189B2 Methods for fabricating silicon carriers with conductive through-vias with low stress and low defect density
有权
用于制造具有低应力和低缺陷密度的导电通孔的硅载体的方法
- Patent Title: Methods for fabricating silicon carriers with conductive through-vias with low stress and low defect density
- Patent Title (中): 用于制造具有低应力和低缺陷密度的导电通孔的硅载体的方法
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Application No.: US11620423Application Date: 2007-01-05
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Publication No.: US07863189B2Publication Date: 2011-01-04
- Inventor: Veeraraghaven S. Basker , John Michael Cotte , Hariklia Deligianni , John Ulrich Knickerbocker , Keith T. Kwietniak
- Applicant: Veeraraghaven S. Basker , John Michael Cotte , Hariklia Deligianni , John Ulrich Knickerbocker , Keith T. Kwietniak
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
Methods are provided for fabricating silicon carriers with conductive through-vias that allow high-yield manufacture of silicon carrier with low defect density. In particular, methods are provided which enable fabrication of silicon carries with via diameters such as 1 to 10 microns in diameter for a vertical thickness of less than 10 micrometers to greater than 300 micrometers, which are capable robust to thermal-mechanical stresses during production to significantly minimize the thermal mechanical movement at the via sidewall interface between the silicon, insulator, liner and conductor materials.
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