Invention Grant
- Patent Title: Integrated circuit fabrication process using a compression cap layer in forming a silicide with minimal post-laser annealing dopant deactivation
- Patent Title (中): 在最小的后激光退火掺杂剂钝化中使用压缩盖层形成硅化物的集成电路制造工艺
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Application No.: US11836326Application Date: 2007-08-09
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Publication No.: US07863193B2Publication Date: 2011-01-04
- Inventor: Yi Ma , Philip Allan Kraus , Christopher Sean Olsen , Khaled Z. Ahmed , Abhilash J. Mayur
- Applicant: Yi Ma , Philip Allan Kraus , Christopher Sean Olsen , Khaled Z. Ahmed , Abhilash J. Mayur
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Law Office of Robert M. Wallace
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
Post-laser annealing dopant deactivation is minimized by performing certain silicide formation process steps prior to laser annealing. A base metal layer is deposited on the source-drain regions and the gate electrode, followed by deposition of an overlying compression cap layer, to prevent metal agglomeration at the silicon melting temperature. Thereafter, a rapid thermal process is performed to heat the substrate sufficiently to form metal silicide contacts at the top surfaces of the source-drain regions and of the gate electrode. The method further includes removing the remainder of the metal-containing layer and then depositing an optical absorber layer over the substrate prior to laser annealing near the silicon melting temperature.
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