Invention Grant
- Patent Title: Efficient transistor structure
- Patent Title (中): 高效晶体管结构
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Application No.: US11586470Application Date: 2006-10-25
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Publication No.: US07863657B2Publication Date: 2011-01-04
- Inventor: Sehat Sutardja
- Applicant: Sehat Sutardja
- Applicant Address: BB St. Michael
- Assignee: Marvell World Trade Ltd.
- Current Assignee: Marvell World Trade Ltd.
- Current Assignee Address: BB St. Michael
- Main IPC: H01L29/72
- IPC: H01L29/72
Abstract:
An integrated circuit comprises a first drain region having a symmetric shape across at least one of horizontal and vertical centerlines. A first gate region has a first shape that surrounds the first drain region. A second drain region has the symmetric shape. A second gate region has the first shape that surrounds the second drain region. A connecting gate region connects the first and second gate regions. A first source region is arranged adjacent to and on one side of the first gate region, the second gate region and the connecting gate region. A second source region is arranged adjacent to and on one side of side of the first gate region, the second gate region and the connecting gate region.
Public/Granted literature
- US20070037353A1 Efficient transistor structure Public/Granted day:2007-02-15
Information query
IPC分类:
