Invention Grant
- Patent Title: Methods and systems for packaging integrated circuits
- Patent Title (中): 集成电路封装的方法和系统
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Application No.: US12789348Application Date: 2010-05-27
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Publication No.: US07863757B2Publication Date: 2011-01-04
- Inventor: You Chye How , Shee Min Yeong
- Applicant: You Chye How , Shee Min Yeong
- Applicant Address: US CA Santa Clara
- Assignee: National Semiconductor Corporation
- Current Assignee: National Semiconductor Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Beyer Law Group LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40

Abstract:
Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts. Dice are mounted onto each device area and electrically connected to the array of contacts. The surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including saw street structures, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable.
Public/Granted literature
- US20100237487A1 METHODS AND SYSTEMS FOR PACKAGING INTEGRATED CIRCUITS Public/Granted day:2010-09-23
Information query
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