Invention Grant
- Patent Title: Adaptive test time reduction for wafer-level testing
- Patent Title (中): 晶圆级测试的自适应测试时间缩短
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Application No.: US12604131Application Date: 2009-10-22
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Publication No.: US07863923B2Publication Date: 2011-01-04
- Inventor: Fidel Muradali
- Applicant: Fidel Muradali
- Applicant Address: US CA Santa Clara
- Assignee: National Semiconductor Corporation
- Current Assignee: National Semiconductor Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Dergosits & Noah LLP
- Main IPC: G01R31/26
- IPC: G01R31/26
Abstract:
In a method for testing a plurality of consecutively indexed sites, a default test sequence is applied to the consecutively indexed sites until a first defective site is identified. If a first defective site is identified, then a more stringent test sequence is applied to a predefined number of sites subsequent to the first defective site. If the more stringent test sequence does not identify a second defective site in the predefined number of sites subsequent to the first defective site, then the default test sequence is resumed.
Public/Granted literature
- US20100052725A1 ADAPTIVE TEST TIME REDUCTION FOR WAFER-LEVEL TESTING Public/Granted day:2010-03-04
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