Invention Grant
- Patent Title: Test circuit, wafer, measuring apparatus, and measuring method
- Patent Title (中): 测试电路,晶圆,测量仪器和测量方法
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Application No.: US11857444Application Date: 2007-09-19
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Publication No.: US07863925B2Publication Date: 2011-01-04
- Inventor: Shigetoshi Sugawa , Akinobu Teramoto
- Applicant: Shigetoshi Sugawa , Akinobu Teramoto
- Applicant Address: JP Miyagi
- Assignee: National University Corporation Tohoku University
- Current Assignee: National University Corporation Tohoku University
- Current Assignee Address: JP Miyagi
- Agency: Jianq Chyun IP Office
- Main IPC: G01R31/26
- IPC: G01R31/26

Abstract:
There is provided a wafer on which a plurality of electronic devices and circuits under test are to be formed, where each circuit under test includes a plurality of transistors under measurement provided in electrically parallel, a selecting section which sequentially selects the respective transistors under measurement, and an output section which sequentially outputs the source voltages of the transistors under measurement sequentially selected by the selecting section.
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