Invention Grant
- Patent Title: Clock frequency dividing circuit
- Patent Title (中): 时钟分频电路
-
Application No.: US12199168Application Date: 2008-08-27
-
Publication No.: US07863948B2Publication Date: 2011-01-04
- Inventor: Hisakatsu Yamaguchi , Kouichi Kanda , Junji Ogawa , Hirotaka Tamura
- Applicant: Hisakatsu Yamaguchi , Kouichi Kanda , Junji Ogawa , Hirotaka Tamura
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Fujitsu Patent Center
- Main IPC: H03B19/00
- IPC: H03B19/00

Abstract:
A first frequency dividing circuit and a second frequency dividing circuit are provided, and these circuits frequency-divide two-phase external clocks injected from an external part, to output four-phase clocks with phase guarantee. Each of the frequency dividing circuits includes a mixer, an adding circuit, and a phase circuit. The first frequency dividing circuit and the second frequency dividing circuit are coupled in loop shape via a first coupling circuit and a second coupling circuit. The first coupling circuit receives a first output signal of the first frequency dividing circuit to output a second external input signal to the second frequency dividing circuit, and the second coupling circuit receives a second output signal of the second frequency dividing circuit to output a first external input signal to the first frequency dividing circuit, and a clock frequency dividing circuit with a high loop gain and a wide lock range can be realized.
Public/Granted literature
- US20090027091A1 CLOCK FREQUENCY DIVIDING CIRCUIT Public/Granted day:2009-01-29
Information query