Invention Grant
US07863962B2 High voltage CMOS output buffer constructed from low voltage CMOS transistors
有权
由低压CMOS晶体管构成的高压CMOS输出缓冲器
- Patent Title: High voltage CMOS output buffer constructed from low voltage CMOS transistors
- Patent Title (中): 由低压CMOS晶体管构成的高压CMOS输出缓冲器
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Application No.: US12148224Application Date: 2008-04-17
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Publication No.: US07863962B2Publication Date: 2011-01-04
- Inventor: Ronald Pasqualini
- Applicant: Ronald Pasqualini
- Applicant Address: US CA Santa Clara
- Assignee: National Semiconductor Corporation
- Current Assignee: National Semiconductor Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Mark C. Pickering
- Main IPC: H03L5/00
- IPC: H03L5/00

Abstract:
A high voltage CMOS output buffer is constructed from low voltage CMOS transistors. The output buffer employs a series of unique CMOS inverter stages, each of which contains a switched PMOS transistor, one or more voltage drop blocks, and a switched NMOS transistor. The voltage drop blocks are composed of stacked PMOS transistors that are diode-connected—i.e., the PMOS gate terminal is connected to the PMOS drain terminal, and the PMOS body (N-well) terminal is connected to the PMOS source terminal. The diode-connected PMOS transistors reduce the voltage across the transistor gate oxide to a safe value, for all internal PMOS/NMOS transistors inside the CMOS output buffer.
Public/Granted literature
- US20090261865A1 High voltage CMOS output buffer constructed from low voltage CMOS transistors Public/Granted day:2009-10-22
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