A circuit comprises first and second inverters, first, second, third, and fourth transistors, and an enabling circuit. The first and second inverters each have an input terminal for receiving one of the first or second input signals, an output terminal, and first and second supply terminals. The first transistor is coupled to a first power supply terminal, to the output terminal of the second inverter, and to the first inverter. The second transistor is coupled to the first power supply terminal, to the output terminal of the first inverter, and to the first supply terminal of the second inverter. The third and fourth transistor are coupled to the second supply terminals of the first and second inverters, respectively, and each includes a control electrode and a second current electrode. The enabling circuit is for controlling the third and fourth transistors to reduce a leakage current in the circuit.