Invention Grant
- Patent Title: Power supply voltage dropping circuit using an N-channel transistor output stage
- Patent Title (中): 使用N沟道晶体管输出级的电源降压电路
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Application No.: US12435780Application Date: 2009-05-05
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Publication No.: US07863969B2Publication Date: 2011-01-04
- Inventor: Ryohei Furuya , Yoji Idei
- Applicant: Ryohei Furuya , Yoji Idei
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2008-128587 20080515
- Main IPC: G05F1/563
- IPC: G05F1/563 ; H02M3/00

Abstract:
A device includes an N-channel transistor for output, a voltage raising circuit, a voltage dropping circuit, and an amplifier. A power supply voltage that is a first voltage is supplied to one end of the output N-channel transistor, and the other end of the output N-channel transistor functions as an output terminal. The voltage raising circuit raises the first voltage to generate a second voltage higher than the first voltage. The voltage dropping circuit reduces the second voltage to generate a third voltage that is higher than the first voltage and is lower than the second voltage. The amplifier amplifies the difference between a reference voltage and a voltage generated at the output terminal, using the third voltage as a power supply voltage, to generate a fourth voltage, and supplies the fourth voltage to the gate of the N-channel transistor for output.
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