Invention Grant
- Patent Title: Techniques for improving balun loaded-Q
- Patent Title (中): 增加平衡 - 不平衡变压器的技术Q
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Application No.: US12189756Application Date: 2008-08-11
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Publication No.: US07863986B2Publication Date: 2011-01-04
- Inventor: Chiewcharn Narathong , Sankaran Aniruddhan
- Applicant: Chiewcharn Narathong , Sankaran Aniruddhan
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporation
- Current Assignee: QUALCOMM Incorporation
- Current Assignee Address: US CA San Diego
- Agent Jiayu Xu
- Main IPC: H03F3/04
- IPC: H03F3/04

Abstract:
Techniques for improving the quality factor (“Q”) of a balun in the presence of loading stages are disclosed. In an exemplary embodiment, the ground node of a balun secondary (single-ended) element is connected to a source node of an amplifier stage via a common ground node. The connection may be made physically short to minimize any parasitic elements. In another exemplary embodiment, the common ground node may be coupled to an off-chip ground voltage via a peaking inductor. The peaking inductor may be implemented on-chip, e.g., as a spiral inductor, or off-chip e.g., using bondwires.
Public/Granted literature
- US20100033253A1 TECHNIQUES FOR IMPROVING BALUN LOADED-Q Public/Granted day:2010-02-11
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