Invention Grant
- Patent Title: Capacitors with low equivalent series resistance
- Patent Title (中): 具有低等效串联电阻的电容器
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Application No.: US11850633Application Date: 2007-09-05
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Publication No.: US07864507B2Publication Date: 2011-01-04
- Inventor: Patrick Franz Fleig , Charles D. E. Lakeman , Mark Fuge
- Applicant: Patrick Franz Fleig , Charles D. E. Lakeman , Mark Fuge
- Applicant Address: US NM Albuquerque
- Assignee: TPL, Inc.
- Current Assignee: TPL, Inc.
- Current Assignee Address: US NM Albuquerque
- Agency: Peacock Myers, P.C.
- Agent Philip D. Askenazy
- Main IPC: H01G9/00
- IPC: H01G9/00

Abstract:
An electric double layer capacitor (EDLC) in a coin or button cell configuration having low equivalent series resistance (ESR). The capacitor comprises mesh or other porous metal that is attached via conducting adhesive to one or both the current collectors. The mesh is embedded into the surface of the adjacent electrode, thereby reducing the interfacial resistance between the electrode and the current collector, thus reducing the ESR of the capacitor.
Public/Granted literature
- US20090168305A1 Capacitors with Low Equivalent Series Resistance Public/Granted day:2009-07-02
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