Invention Grant
US07864561B2 Cell structure with buried capacitor for soft error rate improvement
有权
具有埋入式电容器的电池结构,可提高软错误率
- Patent Title: Cell structure with buried capacitor for soft error rate improvement
- Patent Title (中): 具有埋入式电容器的电池结构,可提高软错误率
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Application No.: US11495369Application Date: 2006-07-28
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Publication No.: US07864561B2Publication Date: 2011-01-04
- Inventor: Jhon Jhy Liaw
- Applicant: Jhon Jhy Liaw
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Tung & Associates
- Main IPC: G11C11/00
- IPC: G11C11/00

Abstract:
A semiconductor memory device with an improved protection against soft errors includes a bi-stable flip-flop cell having a data storage node and a data bar storage node. A first capacitor electrically couples the data storage node to a predefined voltage and a second capacitor electrically couples the data bar storage node to the predefined voltage. Each one of the first and second capacitors includes a top conductive electrode overlying a bottom contact electrode with a dielectric layer disposed in-between. The bottom contact electrode overlays at least two different active regions forming the data and data bar storage nodes.
Public/Granted literature
- US20080025092A1 New cell structure with buried capacitor for soft error rate improvement Public/Granted day:2008-01-31
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