Invention Grant
US07864561B2 Cell structure with buried capacitor for soft error rate improvement 有权
具有埋入式电容器的电池结构,可提高软错误率

Cell structure with buried capacitor for soft error rate improvement
Abstract:
A semiconductor memory device with an improved protection against soft errors includes a bi-stable flip-flop cell having a data storage node and a data bar storage node. A first capacitor electrically couples the data storage node to a predefined voltage and a second capacitor electrically couples the data bar storage node to the predefined voltage. Each one of the first and second capacitors includes a top conductive electrode overlying a bottom contact electrode with a dielectric layer disposed in-between. The bottom contact electrode overlays at least two different active regions forming the data and data bar storage nodes.
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