Invention Grant
- Patent Title: Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells
-
Application No.: US12551936Application Date: 2009-09-01
-
Publication No.: US07864592B2Publication Date: 2011-01-04
- Inventor: Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
- Applicant: Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
- Applicant Address: JP Minato-ku, Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Minato-ku, Tokyo
- Agency: Banner & Witcoff, Ltd
- Priority: JP11-275327 19990928; JP11-345299 19991203
- Main IPC: G11C16/06
- IPC: G11C16/06

Abstract:
Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.
Public/Granted literature
Information query