A reconfigurable multi-code correlation unit for correlating a sequence of chip samples comprising 1) a memory for storing the chip samples; 2) a plurality of add-subtract cells, each add-subtract cell receiving a plurality of real bits, a, and a plurality of imaginary bits, b, from a first chip sample and storing each real bit, a, and each imaginary bit, b, in a data store; and 3) a plurality of sign select units. Each sign select units receives from one add-subtract cell a plurality of first inputs equal to a sum (a+b) of the real bits, a, and the imaginary bits, b, and a plurality of second inputs equal to a difference (a−b) of the real bits, a, and the imaginary bits, b. Each sign select unit generates a plurality of real outputs and a plurality of imaginary outputs, wherein each of the real and imaginary outputs is equal to one of 1) the sum (a+b) multiplied by one of +1 and −1 and 2) the difference (a−b) multiplied by one of +1 and −1.