Disclosed is an arrangement for testing an embedded circuit as part of a whole circuit located on a semiconductor wafer. Disclosed is an integrated semiconductor arrangement comprising a whole circuit (8) with inputs and outputs (7), an embedded circuit (1) that is part of the whole circuit (8) and is equipped with embedded inputs and outputs which are not directly connected to the inputs and outputs (7) of the whole circuit (8); a test circuit (2, 5, 6) that is connected to the embedded inputs and outputs in order to feed and read out signals during a test phase. A separate supply voltage connection (3) is provided which is used for separately supplying the embedded circuit (1) and the test circuit (2, 5, 6) independently of a supply voltage of the whole circuit (8) such that the inputs of the whole circuit do not have to be connected for testing the embedded circuit while only the inputs and outputs that are absolutely indispensable for testing the embedded circuit need to be connected to a test system.