Invention Grant
- Patent Title: System and method for system-on-chip interconnect verification
- Patent Title (中): 系统级芯片互连验证的系统和方法
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Application No.: US11819748Application Date: 2007-06-28
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Publication No.: US07865789B2Publication Date: 2011-01-04
- Inventor: Serafino Bueti , Adam Courchesne , Kenneth J. Goodnow , Gregory J. Mann , Jason M. Norman , Stanley B. Stanski , Scott T. Vento
- Applicant: Serafino Bueti , Adam Courchesne , Kenneth J. Goodnow , Gregory J. Mann , Jason M. Norman , Stanley B. Stanski , Scott T. Vento
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: McGinn Intellectual Property Law Group, PLLC
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.
Public/Granted literature
- US20080215945A1 System and method for system-on-chip interconnect verification Public/Granted day:2008-09-04
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