Invention Grant
- Patent Title: Capacitance extraction of intergrated circuits with floating fill
- Patent Title (中): 集成电路的电容提取与浮动填充
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Application No.: US11369565Application Date: 2006-03-06
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Publication No.: US07865851B2Publication Date: 2011-01-04
- Inventor: David J. Gurney
- Applicant: David J. Gurney
- Applicant Address: US OR Wilsonville
- Assignee: Mentor Graphics Corporation
- Current Assignee: Mentor Graphics Corporation
- Current Assignee Address: US OR Wilsonville
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/45
Abstract:
The present invention improves the accuracy of parasitic capacitance extraction of IC designs with floating fill. One embodiment of the present invention approximates the coupling capacitances of fill nets beyond an exact-approximation level by a fill net elimination method whereby actual capacitances of the fill net to the variable level are fully extracted and remaining capacitances are approximated.
Public/Granted literature
- US20070220459A1 Capacitance extraction of intergrated circuits with floating fill Public/Granted day:2007-09-20
Information query
