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US07865860B2 Layout design device and layout method 失效
布局设计和布局方法

  • Patent Title: Layout design device and layout method
  • Patent Title (中): 布局设计和布局方法
  • Application No.: US12059307
    Application Date: 2008-03-31
  • Publication No.: US07865860B2
    Publication Date: 2011-01-04
  • Inventor: Tomoki Sawano
  • Applicant: Tomoki Sawano
  • Applicant Address: JP Tokyo
  • Assignee: NEC Corporation
  • Current Assignee: NEC Corporation
  • Current Assignee Address: JP Tokyo
  • Priority: JP2007-090032 20070330
  • Main IPC: G06F17/50
  • IPC: G06F17/50
Layout design device and layout method
Abstract:
A layout design device according to an exemplary aspect of the present invention is a layout design device for designing layout of an integrated circuit, including a routing section for adjacently wiring a signal line having a high activity rate and a signal line having a low activity rate based on an activity rate of the signal line of each circuit element.
Abstract(Chinese):

根据本发明的示例性方面的布局设计装置是用于设计集成电路布局的布局设计装置，包括用于相邻布线具有高活动率的信号线的路由部分和具有低活动率的信号线 基于每个电路元件的信号线的活动率。

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