Invention Grant
US07867826B2 Semiconductor device packaged into chip size and manufacturing method thereof
有权
封装成芯片尺寸的半导体器件及其制造方法
- Patent Title: Semiconductor device packaged into chip size and manufacturing method thereof
- Patent Title (中): 封装成芯片尺寸的半导体器件及其制造方法
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Application No.: US12218685Application Date: 2008-07-17
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Publication No.: US07867826B2Publication Date: 2011-01-11
- Inventor: Takeshi Wakabayashi , Ichiro Mihara
- Applicant: Takeshi Wakabayashi , Ichiro Mihara
- Applicant Address: JP Tokyo
- Assignee: Casio Computer Co., Ltd.
- Current Assignee: Casio Computer Co., Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Holtz, Holtz, Goodman & Chick, P.C.
- Priority: JP2004-270646 20040917; JP2005-100737 20050331
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A semiconductor device includes a semiconductor substrate having an integrated circuit and at least one connection pad, and at least one external connection electrode electrically connected with the connection pad. A first sealing material is provided on the semiconductor substrate around the external connection electrode, each impurity concentration of an Na ion, a K ion, a Ca ion and Cl ion contained in the first sealing material being not greater than 10 ppm. A second sealing material is provided on at least one of a lower surface and a peripheral side surface of the semiconductor substrate, a total impurity concentration of an Na ion, a K ion, a Ca ion and a Cl ion contained in the second sealing material being not smaller than 100 ppm.
Public/Granted literature
- US20080286903A1 Semiconductor device packaged into chip size and manufacturing method thereof Public/Granted day:2008-11-20
Information query
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