Invention Grant
- Patent Title: Integrated circuit system for suppressing short channel effects
- Patent Title (中): 用于抑制短信道效应的集成电路系统
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Application No.: US12040777Application Date: 2008-02-29
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Publication No.: US07867835B2Publication Date: 2011-01-11
- Inventor: Jae Gon Lee , Elgin Kiok Boone Quek , Young Way Teh , Wenzhi Gao
- Applicant: Jae Gon Lee , Elgin Kiok Boone Quek , Young Way Teh , Wenzhi Gao
- Applicant Address: SG Singapore
- Assignee: Chartered Semiconductor Manufacturing Ltd.
- Current Assignee: Chartered Semiconductor Manufacturing Ltd.
- Current Assignee Address: SG Singapore
- Agent Mikio Ishimaru
- Main IPC: H01L27/088
- IPC: H01L27/088

Abstract:
An integrated circuit system that includes: providing a substrate including an active device with a gate and a gate dielectric; forming a first liner, a first spacer, a second liner, and a second spacer adjacent the gate; forming a material layer over the integrated circuit system; forming an opening between the material layer and the first spacer by removing a portion of the material layer, the second spacer, and the second liner to expose the substrate; and forming a source/drain extension and a halo region through the opening.
Public/Granted literature
- US20090218636A1 INTEGRATED CIRCUIT SYSTEM FOR SUPPRESSING SHORT CHANNEL EFFECTS Public/Granted day:2009-09-03
Information query
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