Invention Grant
- Patent Title: Method of fabricating power semiconductor device
- Patent Title (中): 制造功率半导体器件的方法
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Application No.: US12507808Application Date: 2009-07-23
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Publication No.: US07867854B2Publication Date: 2011-01-11
- Inventor: Wei-Chieh Lin , Hsin-Yu Hsu , Guo-Liang Yang , Jen-Hao Yeh
- Applicant: Wei-Chieh Lin , Hsin-Yu Hsu , Guo-Liang Yang , Jen-Hao Yeh
- Applicant Address: TW Hsinchu Science Park, Hsin-Chu
- Assignee: Anpec Electronics Corporation
- Current Assignee: Anpec Electronics Corporation
- Current Assignee Address: TW Hsinchu Science Park, Hsin-Chu
- Agent Winston Hsu; Scott Margo
- Priority: TW98115269A 20090508
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
Wider and narrower trenches are formed in a substrate. A first gate material layer is deposited but not fully fills the wider trench. The first gate material layer in the wider trench and above the substrate original surface is removed by isotropic or anisotropic etching back. A first dopant layer is formed in the surface layer of the substrate at the original surface and the sidewall and bottom of the wider trench by tilt ion implantation. A second gate material layer is deposited to fully fill the trenches. The gate material layer above the original surface is removed by anisotropic etching back. A second dopant layer is formed in the surface layer of the substrate at the original surface by ion implantation. The dopants are driven-in to form a base in the substrate and a bottom-lightly-doped layer surrounding the bottom of the wider trench and adjacent to the base.
Public/Granted literature
- US20100285646A1 Method of fabricating power semiconductor device Public/Granted day:2010-11-11
Information query
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